1. Field of the Invention
The present invention relates to a phase synchronization (PLL: Phase Locked Loop) circuit used for a communication apparatus for reception and transmission, such as a TV set, a mobile phone, etc. and an optical disc apparatus, etc., and an electronic apparatus having the phase synchronization circuit.
2. Description of Related Art
For example, a phase synchronization (PLL: Phase Locked Loop) circuit may be incorporated in electronic devices, such as various types of communication apparatuses, and transmission/reception apparatuses or optical disc apparatuses.
FIG. 40 is a circuit block diagram generally showing a phase synchronization circuit. A structure of a phase synchronization circuit 100Z as shown in FIG. 40 also generalizes and illustrates a structure disclosed in non-patent literatures 1-3 to be described later.
As shown, the phase synchronous circuit 100Z includes an oscillation unit 101 for generating an output oscillation signal Vout of an oscillation frequency fosci based on an oscillation control signal CN, and a frequency division unit 102 for dividing the oscillation frequency fosci of the output oscillation signal Vout outputted from the oscillation unit 101 into 1/α, and for acquiring a frequency-divided oscillation signal Vout1.
Further, the phase synchronization circuit 100Z includes a phase comparison unit 103 for comparing phases between an input signal Vin and the output oscillation signal Vout from the oscillation unit 101 or the frequency-divided oscillation signal Vout1 from frequency division unit 102, to output an error signal indicative of a phase difference which is a comparison result as a comparison result signal Vcomp, a current output type drive unit 104Z (hereafter referred to as charge pump unit 104) for outputting and inputting a charge pump current Icp according to the comparison result signal Vcomp outputted from the phase comparison unit 103, and at least a capacitor (capacitance element) 164 of loop filter capacitance Cp, and further provided with a loop filter unit 106 for generating the oscillation control signal CN for controlling the oscillation frequency fosci of the oscillation unit 101 by using the charge voltage Vcp of the capacitor 164 based on the charge pump current Icp from the charge pump unit 104. In this example of structure, the loop filter unit 106 is also provided with a voltage/current conversion unit 166 which converts the charge voltage Vcp of the capacitor 164 into oscillation control current Icnt so that it may correspond to the oscillation unit 101 being a current control oscillation unit 101A.
In the phase synchronization circuit 100Z of such a structure, the input signal Vin and the output oscillation signal Vout from the oscillation unit 101 (or frequency-divided oscillation signal Vout1 by means of the frequency division unit 102) are inputted into the phase comparison unit 103. Based on the comparison result signal Vcomp which indicates the phase error, the oscillation unit 101 is oscillated by way of a technique of the charge pump PLL and the output oscillation signal Vout phase-locked to the input signal Vin is acquired.
Here, linearized closed loop transfer function is generally used for the analysis of the charge pump PLL. With the charge pump current Icp, the input signal-oscillation frequency conversion gain Kosci of the oscillation unit 101, the loop filter capacitance Cp of the capacitor 164, the conversion gain Klp of the loop filter unit 106, the damping effect Flp of the loop filter unit 106, and the frequency division ratio α of the frequency division unit 102, its zone (natural angle frequency or natural frequency; hereafter simply referred to as zone) ωn and the damping factor ζ can be expressed by equation (1-1) and equation (1-2). The damping effect Flp of the loop filter unit 106 and the conversion gain Klp of the loop filter unit 106 correspond to a structure of the loop filter unit 106 (as will be illustrated in detail in embodiments).
The loop filter unit 106 is shown as an example of the drive unit 104Z here in the case of a charge pump 104CP driven in a current mode. However, by way of a circuit theory, “principle of duality” is effected between current and voltage. Therefore, equation (1-1) and equation (1-2) analyzed in a current mode paying attention to the charge pump current Icp can be expressed by equation (1-3) and equation (1-4) when analyzing them in a voltage mode paying attention to a drive voltage Vdr which drives the loop filter unit 106. Since each of equations (1) is known, the derivation processes of the equations will not be explained hereafter.
                                                                                          ω                  n                                =                                                                            Icp                      ·                      Kosci                      ·                      Klp                                                              Cp                      ·                      α                                                                                                          …                                                      (                                  1                  -                  1                                )                                                                                        ζ                =                                                                            Cp                      ·                      Flp                                        2                                    ⁢                  ω                  ⁢                                                                          ⁢                  n                                                                    …                                                      (                                  1                  -                  2                                )                                                                                                          ω                  ⁢                                                                          ⁢                  n                                =                                                                            Vdr                      ·                      Kosci                      ·                      Klp                                                              Cp                      ·                      α                                                                                                          …                                                      (                                  1                  -                  3                                )                                                                                        ζ                =                                                                            Cp                      ·                      Flp                                        2                                    ⁢                  ω                  ⁢                                                                          ⁢                  n                                                                    …                                                      (                                  1                  -                  4                                )                                                    }                            (        1        )            
However, when the phase synchronization circuit 100Z is actually manufactured by IC (Integrated Circuit; semiconductor integrated circuit), parameters which determine the zone ωn, such as the charge pump current Icp, the conversion gain Klp, and the input signal-oscillation frequency conversion gain Kosci, and the damping factor ζ vary from designed values. Thus, it becomes difficult to set the zone ωn an and the damping factor ζ as desired values. Furthermore, considering that they are used in various places, the zone ωn and the damping factor ζ shift from the preset values further, since each parameter changes also with temperature.
If the zone ωn shifts from the preset value considerably, a period until the output oscillation signal Vout is phase-locked to the input signal Vin, i.e., acquisition time, also changes from a preset value. Then, the design of the whole system using the phase synchronization circuit 100Z becomes difficult, and a jitter increases when the zone ωn is shifted much lower. In order to avoid this problem, a technology of compensating for the manufacture variations and temperature characteristics of the input signal-oscillation frequency conversion gain Kosci becomes indispensable
As an arrangement which can meet such a demand, there is an arrangement proposed in non-patent documents 1-3.
ZHI-MING LIN, KUEI-CHEN HUANG, JUN-DA CHEN, and MEI-YUAN LIAO, “A CMOS VOLTAGE-CONTROLLED OSCILLATOR WITH TEMPERATURE COMPENSATED”, The Second IEEE Asia Pacific Conference on ASICs/Aug. 28-30, 2000, p.p 85-86 (non-patent document 1)
Soon-Seob Lee, Tae-Geun Kim, Jae-Tack Yoo and Soo-Won Kim, “Process-and-temperature compensated CMOS voltage-controlled oscillator for clock generators”, ELECTRONICS LETTERS 16th Oct. 2003, Vol. 39, No. 21, p.p 1484-1485 (non-patent document 2)
Takashi Morie, Shiro Dosho, Kouji Okamoto, Yuji Yamada and Kazuaki Sogawa, “A-90 dBc@10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit”, 2005 Symposium on VLSI Circuits Digest of Technical Papers, p 52˜55 (non-patent document 3)
For example, non-patent document 1 has proposed the following arrangement where a voltage controlled oscillator (VCO; Voltage Controlled Oscillator) is constituted by means of plural stages of delay stages (delay stage) (see FIG. 41A similar to FIG. 1 in this document 1), diode connections between PMOS transistors and NMOS transistors are connected in series to be a load so that a common output voltage of the delay stage may always be constant, to thereby compensate for temperature characteristics (see FIG. 41B similar to FIG. 3 in document 1). FIG. 41A is quoted from FIG. 1 of the non-patent document 1, which shows the whole structure of the VCO. FIG. 41B is quoted from FIG. 3 of the non-patent document 1, which shows the delay stage of the VCO.
Further, non-patent document 2 has proposed the following arrangement where the voltage controlled oscillator (VCO) is constituted by means plural stages of delay cells (delay cell), and current independent of a temperature or manufacture variations is made by means of a circuit so that the current may be bias current for a delay cell (see FIG. 42 similar to FIG. 1 of document 2). FIG. 42 is quoted from FIG. 1 of the non-patent document 2, which shows VCO design to provide both current subtraction bias (CSB) selection and a fixed bias (FB) selection.
Further, non-patent document 3 has proposed the following arrangement where a highly precise bias circuit is provided which does not depend on a temperature change in order for charge pump current to be constant, as well as a gain control amplifier which adjusts a gain with respect to the oscillation control signal CN is provided on the input side of the voltage controlled oscillator (VCO), and the gain of a voltage controlled oscillator (VCO) is measured. By controlling the gain control amplifier with a compensation value according to the result, feedback is provided for an input of the voltage controlled oscillator (see FIG. 43 similar to FIG. 1 of the document 3). FIG. 43 is quoted from FIG. 1 of the non-patent document 3, which shows block diagram of the synthesizer with loop bandwidth calibration.